Job Description
Description
In this position you will join a video codec IP development team as the resident FPGA implementation, bringup, debug and timing closure expert. Our mission at Xilinx is to develop advanced video codec IP supporting HEVC, AV1 and future standards. The IP may be deployed on FPGA devices and boards as an end product and/or hardened for embedded applications. You will help target this IP to current generation (Virtex Ultrascale) and next generation (Versal) FPGAs. In the R&D stage of development you will help to test and debug designs using chipscope for signal tracing, RTL simulation, FW debugger, and other techniques. In the product release stage you will be involved in timing closure and product release cycles. Opportunities to expand area of involvement into writing and debugging embedded FW and/or porting designs to the Versal architecture may exist depending on project roadmap and time and ability of the candidate.
Education and other Requirements
- BSEE + 5 years of experience or MSEE + 4 years of experience, or equivalent
- Expertise working with Xilinx FPGAs and toolflow particularly Vivado/Vitis, including building complex systems from scratch, use of chipscope for debugging, incorporating MicroBlaze embedded processors, place and route optimization for timing closure, working with elaborate AXI interconnect networks, tuning system for efficient DDR access, optimizing for SLR crossings, constraints and other handling of multiple clock domains and more
- Solid RTL (Verilog) design experience to create glue blocks, internal statistic monitoring for debug, and other small modules
- Experience with SDK for programming and debugging FW using the built in debugger
- Comfortable operating in a linux environment
- Python/Perl and tcl or equivalent scripting ability to automate build processes including synthesis, checkout and archiving of databases
- Knowledge of basic video encoding and decoding technology useful but can be learned on the job
