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Middle End Design Engineer

159287
San Jose, CA, United States
Nov 5, 2020

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Job Description

Description

Xilinx is seeking an experienced middle end design engineer to help multiple RTL teams prepare their designs for backend implementation.  The candidate will be responsible for supporting and enhancing Linux regression scripts that fully automate the RTL regression process for several EDA tools.  He/She will train and support RTL development teams in the automated regression flow, debug flow issues, and assist RTL designers in the RTL handoff process.  The engineer will also develop SDC constraints and assist with timing closure actities.  The position requires a mix of EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts).  Ideal candidates will have experience cleaning various RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.  As a middle end engineer, familiarity with both front end (RTL) flows and backend (Synthesis and P&R) flows is expected.  

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Tool Experience (experience with 2 or more of the following is required):

  • Synopsys: Design Compiler
  • Synopsys: Primetime
  • Synopsys: Spyglass RTL LINT
  • Synopsys: Spyglass RTL DFT
  • Mentor: Questa CDC (Zero In)
  • Mentor: Questa RDC
  • Cadence: Conformal Low Power
  • Fishtail: Confirm

Shell Scripting Experience:

  • Proficient with scripting languages: CSH, TCL, Perl, Python
  • Proficient with Cron and LSF job control automation
  • Exposure to Mongodb or other databases is a plus

Experience and Education:

  • Bachelor's degree or equivalent with four years of experience
  • Or, Master's degree or equivalent with two years of experience.
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