Xilinx is seeking an experienced middle end design engineer to help multiple RTL teams prepare their designs for backend implementation. The candidate will be responsible for supporting and enhancing Linux regression scripts that fully automate the RTL regression process for several EDA tools. He/She will train and support RTL development teams in the automated regression flow, debug flow issues, and assist RTL designers in the RTL handoff process. The engineer will also develop SDC constraints and assist with timing closure actities. The position requires a mix of EDA tool competence and TCL-based scripting capability (both in EDA tool environments and stand-alone Linux TCL shell scripts). Ideal candidates will have experience cleaning various RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency. As a middle end engineer, familiarity with both front end (RTL) flows and backend (Synthesis and P&R) flows is expected.
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Tool Experience (experience with 2 or more of the following is required):
Shell Scripting Experience:
Experience and Education: