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Senior Signal Integrity and Power Integrity Engineer

159296
Singapore, Singapore, Singapore
Nov 15, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

We are looking for signal integrity engineer to design and analyze high speed interfaces and power distribution network. The candidate will work with other related design teams to define and design the product to meet power and high speed I/O requirements and help the lab measurement and debug. 

 

Responsibilities:

•             Power integrity analysis for die package and PCB, which includes but not limited to layout extraction, electromagnetic and HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.

•             Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain.  Eye diagram and jitter analysis via Chip-package-board co-simulation.

•             Optimal layer stackup & power plane assignment to minimize voltage noise.

•             Special noise-sensitive power supply analysis and layout guideline.

•             Signal trace length matching and impact to timing.

•             Crosstalk analysis and reduction.

•             Full-wave simulation and model extraction for signal integrity and power integrity analysis.

 

Qualifications:

•             Bachelor's degree in Electrical Engineering or Computer Science with 5+ year experience or Master’s degree with 2+ year experience.

•             Solid background on transmission line theory and in-depth knowledge of electromagnetics, PCB layout and package layout techniques.

•             Experience with SI simulation tools, e.g.  Synopsis HSPICE, Ansys HFSS, Q3D, Cadence PowerSI, PowerDC, and Agilent ADS.

•             Experience with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.

•             Experience in FPGA design is a plus.

•             Self-motivated, teamwork, and good communication skills.

Education Requirements

Years of Experience

 

Bachelor's degree in Electrical Engineering or Computer Science with 5+ year experience or Master’s degree with 2+ year experience.

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