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• Ownership Synthesis and Static timing analysis of Large subsystem , hierarchical and full chip designs
• Interact closely with Design, DFX and Physical Design teams for understanding dependencies, providing feedback and alignment deliveries
• Debug Synthesis, Timing QOR, SDC, Low power, Scan stitching issue
• Deliver Timing Closed database for Tapeout including Noise, Signoff Checklists , Functional/ Timing ECOs
• Create new and/or enhance synthesis/timing methodologies and develop proof of concept testcases, automate and work with CAD to roll out flows
• Should be an Expert with hands on experience in full chip / Subsystem /IP timing closure, Low Power Synthesis, constraints development
• Must have knowledge on RTL/design understanding , Synthesis optimization, SDC, clocking, low power (UPF) and DFT
• Must have good understanding for ASIC physical design flows, with various tools , understanding and scripting experience
• Must have strong debugging skills- timing issues, SDC , clock propagation
• Experience with developing flows, methodologies, jitter, spice simulation is a plus
• Must Worked on multiple tapeouts and projects directly responsible for timing signoff
BE / MS +
Years of Experience