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FPGA Full Chip Timing Engineer

159269
San Jose, CA, United States
Jun 2, 2021

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

As a member of the SOC Timing team, candidate will be working on developing methodologies and designs, to characterize and validate of FPGA Timing files. This role would also require candidate to use SPICE, STA and related tools to generate, debug and validate timing models and correlate timing values to silicon measurements. Candidate will also have an opportunity to participate in single chip and stacked silicon full chip timing model validation and other full chip activities..

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Job Requirements:

  • Experience in Digital Design or Silicon characterization
  • Should be knowledgeable about all the internal blocks of FPGA like DSP, BRAM, I/O etc
  • Good understanding of device technology, custom circuit and digital designs and electrical analysis
  • Strong scripting skills using Perl, Python, C-shell or similar scripting languages.
  • Experience with Xilinx FPGA design / implementation tools is a plus
  • Good analytical, communication, presentation and troubleshooting skills are required

Education Requirements

  • Minimum of a BS with 2+ year of experience or MS degree in Electrical Engineering, Computer Engineering or related equivalent

 

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