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Xilinx is looking for a talented individual to join the DFE Technology team in the position of FPGA System Engineer. This team develops high performance and low cost digital front end (DFE) Radio designs for 5G base stations and DOCSIS RemotePHY applications with Xilinx’s unique RFSoC and Versal products and influences future device architectures. As FPGA System Engineer, you will have the opportunity to work on wireless 5G DFE design, development and system testing which is critical to Xilinx’s growth in sub-6GHz and mmwave 5G applications.
- responsible for design, optimization and testing of communication signal processing algorithms and its fixed precision implementation and test with HDL and embedded C/C++ for Xilinx RFSoC and Versal devices
- responsible for signal processing modeling in MATLAB/Python, writing hardware design using VHDL/Verilog, verifying in HDL simulators, and implementing with Xilinx Vivado tools
- Develop Linux/Petalinux/Yocto based embedded FPGA/SoC solutions
- Validate on FPGA evaluation boards in the lab using RF test equipment
- work closely with team members in US, Europe and India offices
- Candidate will participate in different phases of a project, including architecture, system design, coding, unit testing, integration, board bring-up and maintenance and customer support
- Create internal and external facing detailed documentation (micro-architecture design documents, test specifications, test reports, user guides, etc.)
Technical Skill Requirements
- Must have either a BS or MS in Electrical Engineering, Computer Engineering, Computer Science or Electrical and Computer Engineering/Science
- 8+ yrs of experience designing signal processing solutions in VHDL/Verilog optimizing for high throughput with low power consumption
- Prior experience modeling communications and signal processing algorithms using MATLAB/Python is required
- Experience with gate-level understanding of RTL and synthesis (i.e., understand what RTL looks like/behaves like after it is synthesized into gates/FPGA resources)
- Experience using HDL simulator (Modelsim, VCS, etc) is required
- Experienced using Vivado tools and TCL scripting to optimize implementation on FPGA is highly desired
- Prior experience designing embedded system on Xilinx Zynq SoC/MPSoC devices is a strong advantage
- Familiarity with wireless DFE designs, Digital Predistortion (DPD), crest factor reduction (CFR) systems is highly desirable
- Familiarity with 3GPP Standards and test compliance specifications is desirable
- Excellent written and verbal communication skills in English
- Experience creating internal and/or customer facing detailed documentation