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Layout and Automation Engineer

159169
Hyderabad, India, India
Oct 12, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Layout and Automation Engineer:

 

Master’s/Bachelor’s Degree in Electrical/Electronics engineering with 2-5 years of experience in Analog Mixed Signal Layout. Successful candidate would be responsible for layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. Additionally, you would be responsible for doing automation for layout needs including writing scripts to improve layout productivity. You should have worked on FinFet technology (7nm or below would be advantage) on various analog mixed signal blocks such as PLL, Bandgap, ADC, DAC, SERDES, IO etc. Engineer should be well versed with tools such as Virtuoso/XL/GXL, Calibre etc. You are required to work with circuit designers to meet design specifications. This job requires excellent teamwork, good communication and strong problem solving skill.

 

Job Requirements:

 

  • Responsible for independent planning and execution of layout for various designs in 7nm technology nodes and below
  • Hands on experience in all stages of the design such as Floor planning, Placement, Layout, Physical Verification etc. 
  • Must have Perl, TCL, C-Shell and Skill scripting skills to help out the centralized layout team
  • Sound understanding of ESD and Latch up concepts
  • Experience with Cadence Virtuoso-XL and Mentor Graphics Physical Verification Tools is a must
  • Must be experienced in at least one of the industry standard version control tools such as Cliosoft, DesignSync or I.C. Manage etc.
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks
  • Strong problem solving skills
  • Sound knowledge of device matching, pitch matching, double patterning, Electromigration /IR drop and other Layout Dependent Effects
  • Excellent verbal and written communication skills

Education Requirements

Master’s/Bachelor’s Degree in Electrical/Electronics engineering


Years of Experience

2-5 Years

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