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Senior Manager of SOC Development

159128
San Jose, CA, United States
Oct 5, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

In this highly visible role you will be working across business units to build a SOC with IP from internal and external suppliers.  This is a fast moving and challenging role with many key stakeholders across the company and excellent organization and communication skills are essential.  As the COE (Center of Excellence) for this block you will be responsible for direct management of the SOC integration team as well as the point of contact for all scheduling activities spanning front end, middle end, back end and verification/validation. 

 

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Job Qualifications

  • BSEE or MSEE with 10 years of experience or equivalent
  • At least 5 years of RTL Design experience related to high speed IO Protocols
  • Excellent verbal and written communication skills
  • Excellent organizational skills and attention to detail
  • Experience leading multiple parallel projects with rigid schedules and several IP Vendors
  • Understanding of ARM architecture and APB, AXI, ACE, CHI protocols
  • Good understanding of PCIe protocol, SerDes, PLL, AXI Interconnects
  • Working knowledge of Cache Coherency protocols
  • Experience in designing blocks for an SOC
  • Experience in integrating ASIC IP into SOC
  • Experience with automation using scripting techniques such as PERL, Python or TCL
  • Simulation experience and experience building block level verification suites
  • Experience with synthesis, static timing constraints, analysis & optimization
  • Ability to develop clear and concise engineering documentation and work in a fast paced and dynamic organization
  • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
    Desired Qualifications
  • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
  • Working in design teams distributed over multiple sites
  • Post-silicon validation and debug experience
  • FPGA knowledge and emulation experience
  • Experience with Xilinx ISE or Vivado Design Suite
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