Senior Design Verification Engineer

Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and improve people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Job Description

Description 

This is an exciting opportunity to work in the Xilinx SOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on full chip, system level verification, silicon bring up in the lab  

Responsibilities:

-Create block level verification plan, test plans and subsystem test plan

-Develop block level test bench and tests in UVM methodology including scoreboard.

-Work on subsystem level verification

-Work with designers to get the coverage closure

-Port the block level tests to sub system test bench

-Integrate VIPs as needed

-Work with software, validation and emulation teams as needed.

-Work on other aspects of verification like CDC, gate simulation and formal verification

-Work on lab bring up as needed

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Job Qualifications

• MS with 2+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
• -Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology.
• -Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
• -Good understanding of object oriented programming concepts.
• -Prior experience in working on caching protocols such as ACE and CHI.
• -Prior experience in verifying is system/sub system level involving multiple blocks.
• - -Prior experience with protocols such as AXI, APB, AHB etc.
• -Programming in scripting languages like Python, TCL and Perl.
• -Excellent communication skills
• -Good problem solving skills and analytical ability
• -Familiarity with EDA tools for simulation, debugging, coverage analysis, formal verification, CDC, LINT etc.

• Desirable Qualifications:
• -Understanding of FPGA architecture
• -Prior experience in high speed serial protocols such PCIE, CXL and 10G Ethernet
• --Prior experience in working on caching protocols such as ACE and CHI.
• -Prior experience with ARM based Socs
• -Exposure to formal verification methodologies
• -Understanding of ARM architecture and assembly language programming
• -Prior experience in integrating Verification IPs (VIP) & UVC in verification environment.
• -Prior experience in bringing up gate level simulation and debugging issues.