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Xilinx is looking for a talented individual to join the Wired IP Solutions Group (WISG) in the position of Senior Design Engineer 2. The successful candidate will join our design Verification team developing ASIC and FPGA-based intellectual property (IP) to address the needs of state-of-the-art wired communications systems.
It is expected that the candidate will be experienced in SystemVerilog coding, and advanced verification methodologies such as constraint-random or UVM.. Working knowledge of RTL design and processes would be an asset, as would experience with scripting languages such as Python, Perl and TCL. It would also be desirable for applicants to have experience with wired communications protocols such as Ethernet, OTN and Interlaken.
The successful candidate will have demonstrated their technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.
In addition to strong technical abilities, the position requires excellent written and verbal communication skills that will be utilized for multi-location collaboration, developing test plans and testbench documentations. A desire to mentor and coach junior engineers would be a plus.
- BSEE minimum required
- +7 experience in ASIC/FPGA verification
- Extensive experience in designing and implementing testbenches, coverage closure techniques and regression management flows
- In depth knowledge of modern verification practices including System Verilog, UVM and assertion based test
- Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
- Fluency in Verilog or System Verilog
- Excellent written and verbal communication skills
- Expertise in scripting languages such as Python, Perl and TCL
- Experience in C, C++
- Familiarity with Xilinx tools and flows