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Design Engineer (Contract)

158991
Singapore, Singapore, Singapore
Sep 28, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

The engineer will work as part of a cell library design team, in close collaboration with the design automation teams to develop and enhance the development and regression platforms.

 

The engineer’s main responsibilities are the design and development of advanced technology node standard cell libraries. These libraries contain both traditional and complex standard cells that significantly enhance implementation turnaround time while maintaining circuit performance with improved area/power trade-offs.

 

Cell based design/ Place and Route methodology is playing a more significant role in our deep submicron designs, due to both design complexity and the challenges poised from the process technology. 

 

In this highly visible role, the engineer will be working on multi disciplines, with a critical impact on getting functional products to market quickly. The engineer is to be self-motivated to continuously develop skills and accept a variety of  

responsibilities as part of contributing to the design centre’s success. Also, the engineer is to be able to communicate well and demonstrate a positive learning attitude. 

 

 

Job Description

  • Responsible for developing optimal circuit solutions using advanced technology nodes that enables better design performance, with improved area/power tradeoffs

  • Responsible for developing of standard cell source database and to perform cell modelling, which includes timing, functional and power models etc

  • Responsible for developing and updating the standard cell design regression flows

  • Engage with design teams to understand new library cell requirements such as static timing analysis, EMIR and P&R requirements

  • Maintenance of the standard cell source database and regression platform

  • Verification of functionality, performance, and power of all deliverables

  • Evaluate best in class EDA tools in the industry

     

Skills & Experience

 

  • Have a solid understanding of MOSFET electrical characteristics and experience with transistor level circuit simulators, such as HSPICE and SPECTRE.
  • Understanding of layout at the transistor level in order to effectively work with the mask design team.  Familiarity with reviewing DRC and LVS results an added plus.
  • Understanding or an ability to learn a wide variety of industry standard modeling formats including Liberty (CCS, ECSM, and NLDM), Verilog, LEF, Milkyway, APLs, SPICE.
  • Some scripting experience preferred
  • Familiar with working in Linux environment
  • Familiarity with SKILL programming, load sharing concepts (such as LSF) and version control (such as ICManage) an added plus
  • Experience designing or a solid understanding of standard cell architectures, including state retaining elements like latches and flops is an advantage.     
  • New colleague graduates are welcomed.  Training will be provided.  

   

Interpersonal Skills

 

  • Cooperate and communicate well with the library development and design automation
  • Be self-motivated to continuously develop skills and accept a variety of responsibilities as a part of contributing to the design center’s success
  • Demonstrate a positive attitude and respect for all members of the team
  • Be willing to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems

 

Education Requirements 

 

Minimal a bachelor degree in Electrical and Electronics Engineering, Computer Science or Computer Engineering.

 

 

 

 


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