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Senior Verification Engineer - (NoC/DRAM/Performance)

San Jose, CA, United States
Aug 19, 2020


Job Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. 


Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.




Xilinx Central Products Group (CPG) is seeking Senior Design Verification Engineer, who can provide technical leadership and contribution on Verification of Network-on-Chip (NoC) and high-speed Memory Controller IPs.


The individual will help architect, develop and use simulation and/or formal based verification environments, at block and full-chip level, to prove the functional correctness of Network-on-Chip (NoC), System-level Quality of Service (QoS) and DDR, LPDDR, HBM, RLD, and QDR, Memory Controller IP designs.


Your experience and expertise in developing advance SystemVerilog and UVM based testbench and Automation that can scale with Full-Chip will enable improved quality and execution of Xilinx’s devices.


The individual will also collaborate with Architecture, Design, and Software teams to prove that the system-level architecture requirements are met as part of Pre-Si Functional Verification.


Work includes Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs. 



  • Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.
  • The ideal candidate is one who has a proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS requirements. 
  • Requires strong understanding of AXI protocol, NoC architecture, DRAM memory controllers, especially DDR4/5, LPDDR4/5, and HBM2/2E/3.
  • Requires BS w/ 5+ yrs or MS w/ 3+ yrs or PhD in Electrical Engineering, Computer Engineering or Computer Science or related equivalent.
  • Requires experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip FPGA designs and memory controller IPs.
  • Requires strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
  • Requires  familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
  • Experience with FPGA programming and software is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
  • Experience with silicon debug at the tester and board level is a plus.





Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the


employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry,


physical or mental disability, veteran status, gender Identity or sexual orientation. The self-identification information


requested is not gathered for employment decisions. It is used only for compliance with US Federal laws. Your responses


are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not


be subject to any adverse treatment.


Refer to the Talent Network

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