Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most wide-ranging processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). Our global team is growing, and bold, reciprocal and creative people to help us own the industry transformation to build an adaptable intelligent world. We believe that by adopting diverse ideas, striving for perfection in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
Role is open in IPSE Physical Design group which is responsible for Physical Design (RTL to GDS) of all IP Subsystems like
ARM based Multi-Core Processing subsystems, Safety Processing Subsystems, Platform controllers,
HBM, DDR5, PCIE, Hardware Accelerators, AI Engine subsystem with more than 500cores, NOC etc.
Apart from IP & Sub-systems, new technology exploration like 3Chips, improving Physical Design methodology etc are the key ownership activities of the team.
Every IP has it own challenges be it execution, area, low-power, performance, 7nm technology etc.
The Role defines the implementation methodology, schedule, plan, Assign, delegate, track and lead the delivery.
We are looking for talented SOC/IP design – Sr/Engineering Manager to join our team and be responsible for :
Physical Design (RTL to GDS) of one or multiple IPSE projects,
Building, mentoring and leading a design team,
Direct interactions with various teams like ARCH, RTL, DFX, AnalogIP, Integration, Silicon Validation etc,
Understand the requirements, negotiate, define solutions and decision making for a better efficient designs,
Define Design Implementation Methodology, Schedule, Assign, Track, and be responsible for Designs within the group.
Involves 70% of Time on Technical Management and 30% on Team Management.
Masters/Bachelor's degree in Electrical/ Electronic Engineering with 16+ years of experience in ASIC Design.
Very strong knowledge of Physical design concepts (Syn, Floorplan, PG, PnR, PDV, Timing, Signoff).
Ability to work as part of a team, train and lead the team with technical direction.
Solves technical problems of advanced complexity and conveys/applies solutions
Ability to be agile and make progress during critical situations
Excellent leadership, communication, negotiation and time management skills
Ambitious and ability to motivate a team under critical situations.
Good knowledge of scripting and proficient with Industry EDA tools from SNPS and CDN.
Ability to lead a team of 10+ members, scheduling, resource management etc.
Years of Experience