At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
Xilinx is seeking a talented, self-driven and motivated engineer to join our design development team in Hyderabad. The candidate will be responsible for soft IP/kernel development and verification work. We are looking for smart, creative people who have a passion for solving complex problems.
The ideal candidate should have strong background in Verilog RTL Development, UVM Verification, and Xilinx frameworks, with very good understanding in Perl, Shell, TCL scripting on Linux platform and strong modular coding practices. The candidate should have a solid understanding of SW quality and processes.
- BS or MS in EE with up to 1 year of IP/RTL development experience
- Strong background in Verilog RTL for IP development with working expertise on AXI4 Bus Protocol
- Experience with SystemVerilog and UVM for IP verification
- Working knowledge of Xilinx EDA tools like Vivado and Vivado Simulator
- Proficiency in scripting using Shell/TCL, Perl and Python on Linux platform
- Excellent problem solving skills and willingness to think out of the box
- Experience with production software quality assurance practices, methodologies and procedures
- Excellent communication skills and experience working with global teams
Preferred: Experience in any of these areas:
- FPGAs and FPGA software tool chain
- RTL/HLS Kernel Implementation & Verification flow
- Familiarity with VHDL