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Be part of the IP team of next generation PHY/PLL IPs
Participate in defining specification, testing and verification of the IP components. Contribute to micro-architecture specification for SOC/IP AMS blocks
Participate in Analog Mixed Signal IP Architecture specification reviews
Handle complete responsibility of an entire block starting from Micro-architecture specifications, schematic implementation, floor planning, and layout implementation and sign-off
Work with and Interact with layout, integration, verification and physical design teams
BS with 2+yrs exp or MS in Electrical Engineering, Computer Science or related equivalent
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
Hands-on design experience in performance analog mixed signal circuit blocks such as, IO analog frontend, analog-to-digital (ADC), digital-to-analog (DAC) data converter, , LDO, biasing techniques, op-amps, interpolator circuits.
Experience with the following is a plus: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis.
Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off
Solid understanding of power, area and performance trade-offs in mixed signal IP design
Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy High-frequency design experience
Possess strong analytical/problem solving skills and pronounced attention to details
Must be a self-starter, and able to independently drive tasks to completion