This position reports to Product Characterization Manager and interface with other engineering departments. Xilinx is looking for a highly motivated individual to evaluate the performance, timing requirements, development and continuous improvement of Xilinx MPSOC products.
The ideal candidate has some background in timing closure in FPGA synthesis, placement or routing. We are looking for smart, creative people who have a passion for solving complex problems.
Trainee to be involved in:
1. Semiconductor characterization process and development
2. Define and Implement the necessary automation to facilitate post processing, data analysis, and results summary
3. Participate in methodology development related to block level and chip level timing activity.
Traineeship Programme: Only Singaporeans/Singapore Permanent
Residents fresh graduates from 2019/2020 with a Bachelor Degree in Electrical/Electronic Engineering
Mid-Career Pathways Programme: Only Singaporeans/Singapore
Permanent Residents with a Bachelor Degree in Electrical/Electronic Engineering
- Knowledge of FPGA architecture and FPGA software tool chain including Verilog/VHDL and high-level language like C
- Proficiency in automation scripting in Perl, TCL, or Python
- Strong data analysis skill as well as proficiency on data analysis tool e.g. JMP, Microsoft tools
- Strong design timing closure and debugging skills
- RTL knowledge for content creation & debug, including logic and state machine implementation, and Vivado SW knowledge is a plus
- Good verbal and written communication and presentation skills
Duration of Attachment:
Traineeship Programme: 12 months
Mid-Career Pathways Programme: 9 months