Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute
Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.
Work on digital design integration of clock management
blocks (eg, PLL, DLL) and clock distribution for next generation FPGAs.
Involved in the entire design process including RTL design and functional
verification, schematic generation and/or synthesis, place and route, timing
and electrical verification, and working with test engineers on silicon
verification and characterization.
Education and Experience Requirements:
- BS with 2+ years of exp or MS in Electrical Engineering
or Computer Engineering or related equivalent
- Special Requirements: Must have coursework / advance level
coursework / project background in the following:
- 1) Transistor level and standard cell-based design and
- 2) SPICE and Static Timing Analysis (STA) simulators;
- 3) Programming in Verilog for design and DFT
- 4) Experience with PLL’s
- 5) Knowledge of Perl
- 6) Writing constraints for layout synthesis
- 7) Working with test engineering and silicon