At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world.
ARE YOU bold, collaborative, and creative?
At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.
Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.
If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you!
At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work.
Xilinx has an opening for a Senior Hardware Design Manager in the Central Products Group. This team is designing the future generations high-performance CPU and IO subsystem that is combined with FPGA logic to give unparalleled flexibility to systems designers.
In this highly visible role, you will:
Lead a multi-functional team of RTL, Verification, Physical Design and Application engineers to deliver hardware connectivity features meeting strict functional, timing, area and power requirements. This entails:
Participate in crystallization of requirements
Perform Scope/Schedule/Resources tradeoffs and build project plans
You will lead project execution and report status to Program Management
You will perform reviews of design/documentation/quality-metrics to ensure high quality work.
React to changes in scope or dependencies to keep overall project on track
Guide and review verification plans and execution
Perform design work where necessary to keep the project on schedule
Participate in silicon bring-up for features owned
Specify and Implement Automation to increase design team efficiency
Hire/grow/retain engineers for the design team
BSEE or MSEE with 10 years of experience or equivalent
At least 5 years of RTL Design experience related to high speed IO Protocols
Excellent verbal and written communication skills
Excellent organizational skills and attention to detail
Experience leading multiple parallel projects with rigid schedules and several IP Vendors
Understanding of ARM architecture and APB, AXI, ACE, CHI protocols
Good understanding of PCIe protocol, SerDes, PLL, AXI Interconnects
Working knowledge of Cache Coherency protocols
Experience in designing blocks for an SOC
Experience in integrating ASIC IP into SOC
Experience with automation using scripting techniques such as PERL, Python or TCL
Simulation experience and experience building block level verification suites
Experience with synthesis, static timing constraints, analysis & optimization
Ability to develop clear and concise engineering documentation
Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
Working in design teams distributed over multiple sites
Post-silicon validation and debug experience
FPGA knowledge and emulation experience
Experience with Xilinx ISE or Vivado Design Suite
Join our team and unleash your creative brilliance! At Xilinx, we make the impossible possible. Together we can shape the future and enable great technology that changes the way people live and work.
We are a proud equal opportunity employer committed to a diverse workforce. We do not discriminate on the basis of race, religion, color, national origin, gender identity, sexual orientation, age, marital status, or disability.