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Xilinx is looking for a talented individual to join
the DFE Technology
team in the position of Sr Systems
. This team develops high performance and low cost digital
front end (DFE) Radio designs for 5G base stations and DOCSIS Remote-PHY
applications with Xilinx’s unique RFSoC and Versal products and influences
future device architectures. As Sr. Systems Design Engineer
will have the opportunity to work on, architect Wireless/Wired Communication
embedded systems and develop building blocks required for Digital Front End for
these Communication systems.
· Develop and lead the
integration of DSP blocks related to Digital front end for 4G/5G base-stations.
4G/5G test cases in Xilinx’s Lab and replicate faults reported by customer.
within the team to define detailed design requirements, as well as providing FPGA
based architectural expertise and guidance.
with geographically distributed teams and lead technical activities for
customer trials and deployments.
for writing Matlab and C/C++ to emulate system test conditions
Perform system’s performance analysis, prepare customer presentations with
appropriate system staging.
solutions for customer specific requirements.
· Develops innovative but practical solutions to advanced
technical problems in engineering.Technical Skill Requirements
degree in Electronics Engineering or equivalent preferred
years Communication Systems Engineering or related work experience.
years of hands on experience developing Communication systems on FPGAs.
knowledge of systems engineering concepts (definition and analysis for
requirements, performance, capacity, availability, reliability, scalability,
on experience in designing and implementing Digital Signal Processing blocks
with coding signal processing kernels on DSP processors and/or SIMD and VLIW
processor architectures is a plus.
understanding of cellular systems building blocks, with focus on LTE and 5G.
Experience in integrating these building blocks is required.
experience with designing the 5G wireless solutions a definite plus.
understanding of wireless systems performance and features impact/trade-offs.
in validation with Emulators and FPGA evaluation boards is highly desirable.
of data interfacing protocols eCPRI, AXI-Stream, AXI etc is desirable.
proficiency with scripting language like Perl/Python/Tcl is required.
of formal verification/assertions, LINT and CDC tool is desirable.
- Excellent documentation, presentation and