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Staff Design Verification Engineer

158275
San Jose, CA, United States
Jan 13, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.


Xilinx is looking for an experienced and motivated leader to join DCG  Foundational IP Engineering team. As part of this team, you will play a key role in the design, verification, and implementation of next generation FPGA-based intellectual property (IP) blocks for System Interconnect protocols such as PCI Express, DMA, Networking and other similar protocols.

Come join us and be part of team that delivers world-class products that set the industry standard for quality, ease of use and customer support. In this role, you will be responsible for leading the verification of the next generation IPs for Data Center.



  • Minimum of a BSEE/MSEE with 7 years experience.
  • Strong protocol expertise and implementation experience of PCI-Express or Networking
  • Excellent ability to analyze and debug RTL design issues is required.
  • Functional coverage planning/development skills are required.
  • An object oriented programming language such as C++ or System Verilog are required.
  • Knowledge of serial protocols such as Ethernet, Infiniband  is a plus.
  • Expertise complex random-constraint verification methodology
  • UVM experience is a plus.
  • Verilog HDL is required.
Excellent oral and written communication skills with ability to motivate, mentor and develop a world-class team
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