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Senior Verification Engineer II

158273
San Jose, CA, United States
Jul 24, 2020

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx is looking for a talented individual to join the Data Center Group in the position of Staff Design Engineer. This person will possess a deep knowledge in system level challenges, logic design and strong experience architecting complex IP’s.


Job Description and Skills:

  • This candidate will design, implementation RTL for complex digital blocks using Verilog/System Verilog.
  • This candidate will work closely with Functional Verification teams to support block level verification (constrained-random and/or directed verification environments using System Verilog and UVM).
  • Knowledge of bus protocols like AXI/AHB.
  • Basic understanding of FPGA architecture and customer usage model is a plus.
  • Experience with UVM/OVM and/or Verilog, System Verilog test benches, BFMs and usage of simulation tools/debug environments is preferred.
  • This candidate is expected to have strong scripting skills in Perl, Tcl, Shell and/or other languages.
  • Self-motivated team worker with ability to work in a fast-paced work environment

 

 

 

Education:

  • BS in EE/CE + 9 years of experience, or an MS in EE/CE + 7 years of experience.

 

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