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Senior Design Engineer - Timing Closure

San Jose, CA, United States
May 6, 2020


Job Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.


We have an opening for a Sr Design Engineer in the SoC Timing Closure team. This team is designing and analyzing the future generations high-performance FPGA that is combined with CPU and IO subsystems to give unparalleled flexibility to FPGA consumers.

As a member of SoC Design and Integration team, you will:


  • Own key full chip timing activities, deliver timing and noise signoff meeting the defined requirements
  • Responsible for defining and implementing interface timing coverage. Coordinate and work closely with various engineering groups, including frontend design, CAD, physical design and device software modeling
  • Responsible for deriving ECOs for necessary timing and noise fixes leading to full chip timing closure for the targeted block interfaces
  • Participate in methodology development related to block level and chip level timing signoff.
  • Define and Implement the necessary automation to facilitate timing closure setup and analysis, data manipulation, results summary, timing and noise violation debugging, and ECO generations 

Common Essentials Duties include:

  • Exercises solid analytical problem solving in troubleshooting timing analysis results at block level and chip level
  • Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications

  • Becomes in-house expert in tools and methodologies for block and chip level timing closure





Education Requirements

  • BS with 5+ years of working experience or MS with 3+ years of working experience or PhD in Electrical Engineering or Computer Engineering or equivalent
  • In depth working knowledge of Static Timing Analysis tools and flows, preferably in PrimeTime tool set
  • Basic knowledge of FPGA architecture
  • Proficiency in automation scripting in Perl, TCL, or Python
  • Strong design timing debugging skills
  • Good verbal and written communication and presentation skills 

Desired Qualifications

  • Working knowledge of SOC Design and analysis techniques
  • Experience with industry standard EDA tools for synthesis, physical design and electrical analysis  


Refer to the Talent Network

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