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SerDes Application Design Intern

158100
San Jose, CA, United States
Nov 15, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

As a SerDes Applications team member, you will be providing solutions in transceiver applications and product development in next generation transceivers development.

Responsibilities include:
- FPGA design development for various applications and protocols

- Embedded system development in C or C++
- Work with IP teams and customers for various applications and protocols
- Perform SerDes electrical compliance or debug; examples: PCIe, OIF, and 802.3

- Development of SerDes collateral such as user guides, data sheets and application notes

Education Requirements

 
Completion of Junior (3rd year) student enrolled in a Bachelors in Electrical / Computer Engineering / Engineering Science

 

Qualifications


- Experience in Verilog/VHDL, C/C++, and FPGA design
- Experience in Perl, Python, and Matlab
- Hands-on experience with high-bandwidth oscilloscopes, BERTs and associated lab equipment for SERDES characterization
- Strong written and verbal skills
- Student must be available for 12 months, starting in May 2020 and able to re-locate to San Jose. Shorter internship will not be considered.

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