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Senior RTL Design Engineer

158016
San Jose, CA, United States
Nov 1, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Education Requirements

  1. BS with 5+ years of exp. MS with 3+ years of exp or PhD in Electrical Engineering, Computer Engineering or related equivalent on Digital IP Design for high performance, low power FPGA/SOC designs
  2. Must possess a strong background in RTL Logic design.  Prior experience with high speed digital design for serial protocols is highly desired.
  3. Familiarity with basic FPGA/SoC Architecture, front-end SOC/Digital IPs design flows, including design, simulation, synthesis, and timing analysis/closure and sign-off is highly desired.
  4. Demonstrated proficiency in System Verilog and digital design.
  5. Demonstrated proficiency in high speed System Interconnect Interfaces such as PCI Express is a plus.

    Years of Experience

BS with 5+ years of exp. MS with 3+ years of exp or PhD in Electrical Engineering, Computer Engineering

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