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Senior Packaging Engineer

158012
Singapore, Singapore, Singapore
Nov 28, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.


Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.


Job Responsibilities:


  • Actively participate & lead cross-functional teams for technology risk analysis, mitigation plans, qualification timelines to ensure robust package quality, yield & reliability
  • Direct interface with vendors to generate & maintain design integration documents, process flows, KPIs, risk registers, BOMs, DOEs, build trackers & action items
  • Coordinate EFA/PFA activities, track yield/reliability pareto, data analysis & follow through issue resolution
  • Generate internal & external presentations, technical reports for periodic engineering reviews


 

Qualifications:
  • BS/MS in Materials Science, Mechanical Engineering, Electrical Engineering or other semiconductor packaging related discipline
  • 5+ yrs. experience with advanced microelectronics packaging, Fan out RDL, high performance build-up substrates, 2.5D, MCM, 3D, heterogeneous SIP
  • Deep understanding of MEOL/BEOL process integration, SPC, DOE, material trends, design rules capability for organic & ceramic flip chip package
  • Hands on knowledge of package reliability requirements, industry standards such as JEDEC, IPC, failure analysis techniques, and interpretation of failure modes
  • Experience collaborating with foundries, assembly service providers & subcontractor management is strongly preferred
  • Strong problem solving, communication, organizational, interpersonal, and presentation skills

 

 

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