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Senior Design Engineer

158009
San Jose, CA, United States
Oct 29, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

We have an opening for a Sr Design Engineer in the SoC Timing Team. This team is designing and analyzing the future generations high-performance FPGA that is combined with CPU and IO subsystems to give unparalleled flexibility to FPGA consumers.

 

As a member of SoC Design and Integration team, you will:

  • Own several full chip timing closure activities, including timing and noise signoff for tapeout.
  • Participate in methodology development and implementation related to constraint development, timing budgeting, model validation, data handoffs, and timing debugging.
  • Interface with various engineering groups, including design, CAD, software, and product engineering to guide timing closure activities.

Common Essentials Duties and Responsibilities include:

  • Exercises solid analytical problem solving in troubleshooting timing analysis results for Block level and Chip level designs.
  • Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications
  • Becomes expert in tools and methodologies in design implementation and timing signoff.

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Education Requirements

  • BS with 3+ years of exp or MS 1+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
  • Working experience with Static Timing Analysis tools, preferably PrimeTime tool set
  • Basic knowledge of FPGA architecture
  • Proficiency in automation scripting with Perl, TCL, or Python
  • Strong debugging skills
  • Good verbal and written communication and presentation skills

Desired qualifications

  • Understanding of SOC Design and analysis techniques
  • Experience with industry standard EDA tools for synthesis, physical design and electrical analysis

       


 


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