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Xilinx is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Design Engineer to work on development of next generation highly configurable blocks that operate at over 1 GHz data rate.
The successful candidate will work as a contributing member responsible for the architecture and design of next generation memory interfaces that operate over 6 GHz data rate for Xilinx customers. Responsibilities include RTL development, resolving system level challenges, architecting, implementing, documenting and validating the memory controller IP cores. The area of focus would be on high speed memory interfaces like DDR5, LPDDR5, DDR4, LPDDR4, DDR3, QDR4, LPDDR3 and RLDRAM3. The candidate must have excellent inter-personal and communication skills and be able to work independently.
Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores.
B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3+ years of relevant experience
2+ years of experience in designing complex IP’s
Excellent Verilog and logic design concepts
Experience with automation using scripting techniques such as PERL, Python or TCL
Knowledge of bus protocols like AXI/AHB
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim.
Excellent communication and problem solving skills.
Should have experience working in geographically dispersed team and should be a strong team player