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The SerDes Architecture and Modeling Group has responsibilities in generating robust SerDes architecture and algorithms, creating silicon and system level specifications, developing and verifying SerDes design models, developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon.
We’re looking for a system architect to join a fast paced transceiver design team. Our team stays ahead of the technology curve to deliver world-class programmable transceiver solutions for multiple FPGA platforms, supporting over 20 protocols with thousands of customer applications.
The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas:
Signal processing, data coding, and FEC algorithms
SerDes architecture development including equalizers and time recovery for NRZ and PAM4 systems
Behavioral modeling of different blocks in transceivers
Familiarity with optical link analysis and evaluation is a plus
Presenting design trade-off analyses and implementation recommendations with custom circuit designers
BS with 3+ years of exp. or MS with 1+ year of exp in Electrical Engineering, Computer Engineering or Related Equivalent
Signal modulation, coding, and FEC knowledge and experience
Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred
Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc.
ADC based SerDes architecture experience is a plus
Experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus and familiarity with Simulink/Matlab and C/C++ programming
Experience with lab equipment for high-speed digital systems
Good understanding of high speed signal integrity issues
Excellent technical communication skills (presentations and documentation)