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- responsible for design, optimization and testing of communication signal processing algorithms and its fixed precision implementation and test with matlab and embedded C/C++
- responsible for writing matlab and C/C++ to emulate system test conditions for DFE solutions
- Develop signal processing libraries for Adaptable Intelligent (AI) Engines (Vector Engines) on Xilinx Versal ACAP devices
- Assist with new product/board bring-up and validation on Xilinx SoC devices
- Candidate will participate in different phases of a project, including design, coding, unit testing, integration and maintenance and customer support
- Create internal and external facing detailed documentation (micro-architecture design documents, test specifications, test reports, user guides, etc.)
Technical Skill Requirements
- Masters degree in Computer/Electronics Engineering or equivalent preferred
- 2+ years of experience developing signal processing IP on FPGA, DSP processors and/or SIMD and VLIW processor architectures
- 2+ years of hands on experience in designing signal processing kernels and verifying those in cycle-accurate and bit-true simulators
- Experience validating kernels on boards highly desirable
- Ability to translate a software model into fixed point hardware implementation
- Excellent written and verbal communication skills in English
- Experience creating internal and/or customer facing detailed documentation