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Senior IC Layout Engineer (contract)

157801
Singapore, Singapore, Singapore
Sep 1, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

The Wired Engineering Group designs high speed serial interface systems which are integrated into FPGA devices. These devices are used in a variety of applications such as automotive, wireline and wireless communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques.

 
Successful candidates will work as part of an experienced team executing projects in advanced CMOS manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include: layout of analog and digital circuits. There is the opportunity to contribute to methodology initiatives to accelerate design layout.
 
 
Job Description:
  • Design top quality complex layout for high speed analog mixed signal circuits from sub-blocks to top-level integration.
  • Review and analysing floor plans and complex circuits with circuit designer. 
  • Run a complete set of design verifications
  • Collaborate with the circuit design teams to constantly optimize layout implementation for better power, performance and area, as well as planning on work schedule.
  • Responsible for in-house IP/library developments

The successful incumbent should be/possess the following:
  • Bachelor degree in Electrical & Electronics Engineering or equivalent
  • At least five (5+) years of analog custom IC physical design experience
  • Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is preferred
  • Understanding of cutting edge silicon process technologies (CMOS 16nm and below)
  • Hands-on experience using Cadence and Mentor tools is preferred
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks.
  • Familiarity with circuit design concepts, flow and IC manufacturing processes
  • Understanding of parasitic impact on circuit performance is a plus.
  • Understanding of digital SOC flow is an advantage.
  • Knowledge of scripting languages like SKILL, PERL, TCL etc. is a plus
  • Capacity to take on board new approaches and working methods
  • Strong communication, documentation and analytical skills.
  • Highly motivated, excellent team player and customer oriented.
  • Ability to work across functions, level and remote sites
  • Ability to work outside of official working hours ,if assigned, to support remote design teams is a plus
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