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Staff Verification Engineer

157776
Hyderabad, India, India
Sep 6, 2019

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Job Description

Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.



Verification

  • Ability to define and implement verification methodologies for FPGA/ASIC (SV, UVM)
  • Ability to lead RTL verification tasks for complex FPGA/ASIC designs/complex design blocks by fully understanding the architecture and design specification 
  • Interact with architects and design engineers to create a comprehensive verification test plan
  • Understanding of PCIE/Networking/RDMA Protocols is a Plus
  • Understanding of AMBA protocols like AXI4, AXI-STREAM and AHB is needed.
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality measurements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

  • BS with 9+ years of experience or MS with 6+ years of experience or PhD with 3+ years of experience with a degree in electrical engineering, computer engineering or related equivalent

  • Strong experience in HDL, verification, and general computational logic design/verification concepts

  • Understanding FPGA/ASIC design flows from RTL development, Synthesis, Verification, Validation frontend to backend is a plus.

  • Proficiency in System Verilog and UVM
  • Prior use of simulation tools/debug environments such as Mentor Questa , Synopsys VCS, Cadence IES, is required
  • Proficiency in Perl, Python and/or other scripting language
  • Basic understanding of formal verification/assertions, LINT and CDC tool
  • Excellent interpersonal skills, self-motivated & looking for someone with a growth-mindset 

 

 

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