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From a chip and block specification be able to generate a comprehensive test-plan and UVM test-bench from scratch.
- Execute test-plan to achieve coverage goals. This includes building test cases, functional coverage metrics and coverage analysis.
Generate comprehensive random and directed test cases to deliver functionally correct designs.
Utilize latest tools to collect and identify design coverage holes
Develop C/C++ reference model.
Write tools and scripts to enhance the verification process.
- Work with Design team and Firmware team in system level debug.
- Additional duties and responsibilities as assigned
Working experience of UVM methodology and have applied that methodology on at least one ASIC project.
Strong background in networking protocols like Ethernet and TCP-IP, and verification experience of PCIE protocols.
Typically requires a minimum of 8 years of related experience with a Bachelor's degree; or 6 years and a Master's degree; or a
PhD with 3 years experience; or equivalent experience in EE/CE.
8+ years experience in the ASIC verification methodology, with some experience in emulation platforms is a plus.
5+ years experience in design using SystemVerilog, C/C++ programming and Perl scripting is a plus.
2+ years experience firmware and software driver development is a plus.