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Staff Verification Engineer

Irvine, CA, United States
Aug 25, 2019


Job Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

From a chip and block specification be able to generate a comprehensive test-plan and UVM test-bench from scratch.
  • Develop sophisticated testbench components in SystemVerilog with UVM and C/C++.

  • Execute test-plan to achieve coverage goals. This includes building test cases, functional coverage metrics and coverage analysis.
  • Generate comprehensive random and directed test cases to deliver functionally correct designs.

  • Utilize latest tools to collect and identify design coverage holes

  • Develop C/C++ reference model.

  • Write tools and scripts to enhance the verification process.

  • Work with Design team and Firmware team in system level debug.
  • Additional duties and responsibilities as assigned
  • Working experience of UVM methodology and have applied that methodology on at least one ASIC project.

  • Strong background in networking protocols like Ethernet and TCP-IP, and verification experience of PCIE protocols.

Education Requirements

Typically requires a minimum of 8 years of related experience with a Bachelor's degree; or 6 years and a Master's degree; or a
PhD with 3 years experience; or equivalent experience in EE/CE.


  • 8+ years experience in the ASIC verification methodology, with some experience in emulation platforms is a plus.
  • 5+ years experience in design using SystemVerilog, C/C++ programming and Perl scripting is a plus.

  • 2+ years experience firmware and software driver development is a plus.

Refer to the Talent Network