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Be part of Xilinx’s IP team responsible for R&D/design of next generation clocking/PLLs solutions, next generation IOs, high speed memory (LPDDR4/DDR4, LPDDR5/DDR5, gDDR6, HBM2/HBM3, …), chip-to-chip Gbps proprietary PHY IP solutions. Responsibilities include but not limited to:
1. Be part of the IP team of next generation PHY/PLL IPs. Engage in design architecture to micro-architecture phase
2. Participate in defining specification, testing and verification of the IP components.
3. Perform RTL-level design, including micro-architectural definition, of the digital portions of the IP architecture
4. Work closely with methodology, PD teams to implement RTL design into GDSII.
5. Drive design closure thru synthesis, static-timing analysis, logical equivalency checking. Help improve flows and scripts for such tasks
6. Support post-silicon product bring-up and debug, and sign-off on test-plans and characterization reports.
7. Design support for SOC/FPGA integration teams, system HW/SW teams, and global operations/manufacturing teams.
8. Setup and analysis of lint, synthesis, timing closure and DFT coverage reports
9. Define or participate in micro-architecture definition and drive for power, performance and area (PPA) targets/enhancements
10. Influence the methodology on mixed signal IP flows on simulations, timing closure. Participate in establishing CAD and design methodologies for correct by construction designs.