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Senior Design Engineer

157700
San Jose, CA, United States
Aug 14, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. 

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Overview:

 

The Xilinx Central Engineering Memory Subsystem team is searching for a passionate, adaptable and innovative design engineer to contribute towards the next generation of High-Bandwidth Memory (HBM) Controller(s).

 

 

Job Responsibilities:

  • Create microarchitecture and write RTL
  • Verify intended functionality with block-/unit-level test bench
  • Perform verification, system validation and coordination with other teams
  • Write optimal timing constraints (SDC)
  • Run design sanity checker tools such as LINT, CDC, FishTail, etc.
  • Work closely with physical design team during implementation
  • Document design and effective verbal communication
 Education & Experience:
  • Bachelors/ Masters in Electrical Engineering
  • 7+ years of experience in Verilog/SystemVerilog (ASIC, FPGA, IP)
  • Experience with SDRAM (DDR, HBM) is a plus
  • Scripting in Python, Perl, TCL
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