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PnR CAD flow and methology developement

157651
Hyderabad, India, India
Aug 22, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

 

This position for a CAD Engineer will be critical to shaping the next generation of FPGA products from Xilinx, the leader in FPGAs.  It requires interfacing with large design teams across the globe and owning methodology development for next generation synthesis, place and route flows. Successful candidate would be responsible for automation of PnR flows and methodologies for the 7nm technology node as well as work closely with the EDA vendors to identify innovative solutions and track methodology issues.

 

 Role and Responsibilities:

·         Responsible for developing Place and Route methodologies for various designs at the 7nm technology node

.         Responsible for deploying advanced features such as UPF based low power flow, and hierarchical flow

·         Script out utilities to automate different pieces of the implementation flow

·         Support the design team through multiple PnR flow stages

.        Methodology development or physical implementation on advanced nodes such as 16nm and 7nm is preferred

 

Tool Expertise Required:

·         Good control over scripting languages like Python, PERL, TCL and strong debug capabilities

·         CAD and Automation mindset

·         Hands on experience in synthesis, place and route flows and STA tools

.         Hands on experience in DC, ICC2, Innvous, PrimeTime

·         Hands on experience with physical verification tools

 

 Qualifications and requirements:

·         Master’s/Bachelor’s Degree in Electrical/Electronics engineering

·         2-4 years of experience in CAD flow and methodology development on advanced nodes such as 16nm and 7nm is preferred

·         Should be proficient in Tcl/Perl/XML

·        Work closely with design teams to support multiple areas through RTL to GDSII implementation

.        Support cross site design teams

·         Strong problem solving skills and analytical thinking

·         Excellent communication skills

 

 

 

 

Education Requirements 
 

Master’s/Bachelor’s Degree in Electrical/Electronics engineering

2-4 years of experience in CAD flow and methodology development on advanced nodes   

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