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Senior Design Verification Engineer

157561
San Jose, CA, United States
Oct 23, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Responsibilities:

  • Work closely with design and architecture, across geographies, to develop and understand complex digital designs
  • Take ownership of system/block level verification tasks
  • Define test plans, test benches, and tests using C/System Verilog and UVM to verify the next generation of Xilinx ACAP devices
  • Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes
  • Develop and improve existing verification environments

#mh

 

Qualification:

  • BS with 5+ years of experience or MS with 3+ years of experience or PhD with a degree in electrical engineering, computer engineering or related equivalent
  • Experience with developing UVM and/or system Verilog testbenches
  • Experience with system/sub-system level verification of complex SOCs strongly desired
  • Experience with writing C/C++, assembly tests 
  • Experience with ARM AMBA protocols
  • Knowledge of scripting languages for verification automation
  • Familiarity with verification management and revision control tools
  • Experience with gate level simulation, power and reset verification
  • Excellent documentation and communication skills
  • Strong desire to learn and undertake new challenges  


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