This is an exciting opportunity to work in the Xilinx MPSOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. The candidate will have opportunity to work on sub system level verification besides working on the block level verification.
-Create block level verification plan, test plans and full chip test plan
-Develop block level test bench and tests in UVM methodology including scoreboard.
-Work on subsystem level verification
--Write C based tests to execute on the processors in the sub system.
-Work with designers to get the coverage closure
-Port the block level tests to full chip test bench
-Integrate VIPs as needed
-Work with software, validation and emulation teams as needed.
-Work on other aspects of verification like CDC, gate simulation.
-Work on power aware verification using UPF.
-Assist in the silicon bring up in the lab
-Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology.
-Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
-Familiarity in writing System Verilog Assertions.
-Good understanding of object oriented programming concepts.
-Prior experience in verifying is system/sub system level involving multiple SoC blocks.
-Prior experience with PCIE Express Transport Layer
- Prior experience in high speed serial protocols such PCIE and 10G Ethernet
-Prior experience with protocols such as AXI, APB, AHB ,ACE etc.
-Programming in scripting languages like Python, TCL and Perl.
-Excellent communication skills
-Good problem solving skills and analytical ability
-Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.
--Work with cross functional team such as software drivers, software tools as needed.
-Understanding of FPGA architecture
-Exposure to formal verification methodologies
-Understanding of ARM architecture and assembly language programming
-Prior experience in integrating Verification IPs (VIP) & UVC in verification environment.
-Prior experience in bringing up gate level simulation and debugging issues.
--Familiarity with caching protocols such as MESI, MOSEI
--Prior experience in verification of cache sub systems in processors and/or cache coherent interconnect such as CCI400
Master's Degree in Electrical Engineering or Computer Science with 8-10years of experience Or
Bachelor's Degree in Electrical Engineering or Computer Science with 10 years of experience