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Staff Design Engineer

157539
Hyderabad, India, India
Sep 28, 2019

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Job Description

Description

Senior Design Verification Engineer

Memory Controller & PHY-IO IP Verification 


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

Xilinx’s SAV Verification group is looking for a Design Verification Engineer to contribute on high speed Memory Controller and PHY/IO IP Verification. The individual will help design, develop and use digital simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR, LPDDR, RLDRAM, QDR, HBM Memory Controllers, PHY/IO, and Network On-Chip (NOC) IPs, Subsystem, and SOC designs.

 

Responsibilities: 

  • Plan verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.

  • Create and enhance constrained-random and/or directed verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.

  • Identify and write all types of coverage measures for stimulus quality measurements.

  • Debug tests with design engineers to deliver functionally correct design blocks. 

  • Close coverage measures to identify verification holes and to show progress towards tape-out. 

 Requirements:

  • Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality
  • Require hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, RLDRAM and QDR, and HBM. Requires understanding of current memory controller protocols and calibration, JEDEC specification, board skew and jitter modeling.
  • Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, and Cadence IES to verify memory controller IPs.
  • Require understanding of state-of-the-art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
  • Proficiency in C, Perl, Python and/or other scripting language.
  • Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
  • Experience with FPGA programming and software is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
  • Experience with silicon debug at the tester and board level, is a plus.

Education Requirements
Require BS w/ 6+ yrs or MS w/ 2+ yrs or PhD w/ 2+ yrs in Electrical Engineering, Computer Engineering or Computer Science
Years of Experience
Require BS w/ 6+ yrs or MS w/ 2+ yrs or PhD w/ 2+ yrs
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