Xilinx is looking for a motivated DV engineer to join the DCG Networking engineering team. As part of this team, you will play a key role in the design and verification the next generation FPGA-based intellectual property (IP) blocks for System Interconnect protocols such as PCI Express, DMA, Networking, and other similar protocols.
Come join us and be part of team that delivers world-class products that set the industry standard for quality, ease of use and customer support. In this role, you will be responsible for the design and verification of these interconnect protocol blocks. You will have the opportunity to be a key member of the implementation of FPGA hard IP blocks, as well has companion soft solution IP blocks such as DMA, AXI, Crypto and Machine Learning.
· Excellent ability to analyze and debug RTL design issues is required.
· An object oriented programming language such as C++ or System Verilog are required.
· Knowledge of serial protocols such as Ethernet, PCIe, DMA, AXI, ML is a plus.
· UVM experience is a plus.
· Verilog HDL is required.
· Excellent oral and written communication skills with ability to motivate, mentor and develop a world-class team
· MSEE or BSEE with 2+ years of relevant experience