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As part of Wired Engineering
Working on RTL to GDS, including synthesis, placement, clock tree insertion and routing. Also responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.
Bachelor/Masters Degree in Electrical/Computer Engineering
Minimum 6 to 8 years of relevant experience
Good experience and knowledge in design flow from Netlist to GDS, Floor Plan, Synthesis, route , STA, CTS, RC Extraction and correlation
Static timing analysis, power and noise analysis and back-end verification across multiple projects.
Proficient with backend design EDA tools Synopsys (preferred) or Cadence
Successfully track records of taping out complex SOC
Working knowledge of deep sub-micron routing issues as they relate to power and timing.
Proficient in using TCL and Perl
Self-motivated team worker, good verbal and written communication skills