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Senior Design Engineer II

157440
Singapore, Singapore, Singapore
Jun 20, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

 

As part of Wired Engineering
Working on RTL to GDS, including synthesis, placement, clock tree insertion and routing. Also responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc. Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

 

Bachelor/Masters Degree in Electrical/Computer Engineering
Minimum 6 to 8 years of relevant experience
Good experience and knowledge in design flow from  Netlist to GDS, Floor Plan, Synthesis, route , STA, CTS, RC Extraction and correlation
Static timing analysis, power and noise analysis and back-end verification across multiple projects.
Proficient with backend design EDA tools Synopsys (preferred) or Cadence
Successfully track records of taping out complex SOC
Working knowledge of deep sub-micron routing issues as they relate to power and timing.
Proficient in using TCL and Perl
Self-motivated team worker, good verbal and written communication skills

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