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Senior Design Engineer 1

157410
Hyderabad, India, India
Jun 25, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology.  We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. 


Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.  From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.


If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you!  At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work.  We are ONEXILINX.


The Silicon development team is looking for an experienced verification engineer in Xilinx India, for the verification of next generation Cache Coherency Systems

 

Responsibilities include the following:  

·    Work with Architecture, design, emulation and application teams and contribute to the verification of the next generation of Cache Coherency Systems

·    Play a key role in the development of different verification platforms in System Verilog/UVM including utilization of Emulation/Prototyping platforms for verifying next generation coherent MPSOC FPGA designs

·    Verify the architecture and performance of the design

·    Work with Architecture and Emulation teams to ensure micro-architecture and design is fully verified/validated across multiple platforms

·    Be responsible for a comprehensive verification plan and drive the implementation of verification test cases from applications and other sources

 

Qualifications:

·    Masters in electrical or computer engineering

·    5+ total of which 2+ years of experience in the verification of Processor and Cache Coherency Systems

·    Experience in specifying and developing the verification infrastructure for verifying processor based designs 

·    Understanding of coherency, cache design and protocols

·    Strong analytical problem solving, and attention to details 

·    Strong experience in HDL, verification, and general computational logic design/verification concepts

·    Expertise in Verilog/System Verilog, UVM, Scripting languages like Perl/Python, etc.

·    Excellent written and verbal communication skills

·    Excellent interpersonal skills, self-motivated

 

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