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Senior Design Engineer - SoC/STA

157298
San Jose, CA, United States
May 22, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

 


 

Job Description:

 

We are currently seeking a qualified individual who can contribute to the development of cutting edge design of Xilinx FPGA ICs. Primary job function would be to own and manage both block and SOC level timing closure (STA) for multiple blocks. Candidate must be able to communicate well among design team,partners as well as with overseas groups. Candidate will have experience in writing Primetime constraints, Knowledge of Verilog and System Verilog, Schematic design and simulation, DFT, and a variety of back end flows.


Your primarily responsibility will be Timing Closure (STA) of large SOC subsystems.  Candidate will be willing to perform a wide range of back-end activities such as synthesis of RTL, DFT insertion, power optimization, Floor-planning, Place and Route, Clock Tree Synthesis (CTS), DRC, LVS, Antenna checks, IR drop (RedHawk) and multi voltage checks. You will also work closely with full chip integration team to ensure your sub-systems is fully qualified and signed off at Full-chip level. 

Education & Experience Requirements
BS with 5+ yrs or MS with 3+ yrs experience or PhD with a degree in Computer Engineering, Electrical Engineering or related equivalent

Other Qualifications:
  • Expert in Synopsys Primetime-SI
  • Knowledgeable in ICC2, Design Complier
  • Ability to understand circuit design and write SOC constraints
  • Capable of debugging runs and working with others to help improve flows and methodology
  • Willing to learn and work with internal tool flows
  • Good communication skills and ability to give feedback to designers on how to improve designs for higher performance
  • Ability to communicate with architecture, RTL design and other remote teams
  • Participation in the development of back-end SoC design flows
  • Experience of UPF low power design
  • Previous experience with clock generation circuitry such as MMCM and PLL is a plus
  • Understanding of Analog and custom digital circuits
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