DescriptionXilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
We are currently seeking a qualified individual who can contribute to the development of cutting edge design of Xilinx FPGA ICs. Primary job function would be to own and manage both block and SOC level timing closure (STA) for multiple blocks. Candidate must be able to communicate well among design team,partners as well as with overseas groups. Candidate will have experience in writing Primetime constraints, Knowledge of Verilog and System Verilog, Schematic design and simulation, DFT, and a variety of back end flows.
Your primarily responsibility will be Timing Closure (STA) of large SOC subsystems. Candidate will be willing to perform a wide range of back-end activities such as synthesis of RTL, DFT insertion, power optimization, Floor-planning, Place and Route, Clock Tree Synthesis (CTS), DRC, LVS, Antenna checks, IR drop (RedHawk) and multi voltage checks. You will also work closely with full chip integration team to ensure your sub-systems is fully qualified and signed off at Full-chip level.
Education & Experience Requirements