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Design and develop electronic components. Specifically, work on digital
design of clock management blocks (eg, PLL, DLL) and clock distribution for
next generation FPGAs. Involved in the entire design process including RTL
design and functional verification, schematic generation and/or synthesis,
place and route, timing and electrical verification, and working with test
engineers on silicon verification and characterization.
Should have coursework, advance level coursework, project background, or
experience in the following:
1) Transistor level and standard cell-based design and verification;
2) SPICE and Static Timing Analysis (STA) simulators;
3) Programming in Verilog for design and DFT;
4) Phase Locked Loops (PLL) operation and design;
Following a plus:
1) Reading/Writing scripts in PERL or Python;
2) Writing constraints for STA and layout synthesis; and,
3) Test engineering and silicon debug.
- Master’s degree or foreign equivalent in Electrical Engineering,
- Bachelor's degree in Electrical Engineering with 2-3 years experience
- 1-2 years of experience