Xilinx Edinburgh is adding to its Data Centre design team. This is a fantastic opportunity for an engineer with a passion for algorithmic acceleration on FPGA or other architectures to join a team with access to world-class infrastructure and platforms to work on the next generation of accelerated applications and libraries. You'll work in a recently established team responsible for financial technology applications on Xilinx Alveo platforms, both working on the applications themselves and enhancements to the platforms to enable our customer solutions both on their own premises and in the cloud. In this role you will be developing architectures for hardware/software interaction for acceleration and implementing these architectures in C++ and/or Verilog RTL.
This is an opportunity to work with leading-edge technologies such as Vivado HLS, Ultrascale + and Versal silicon, and Alveo accelerator cards for the data centre.
•Degree or better in Electronic Engineering, Computer science, or related subject
Skills and Experience:
•Experience in algorithmic development and heterogenous computing in a data centre environment is highly desired.
•Experience in high-level synthesis in C, C++ or OpenCL would be beneficial.
•Experience with Verilog and/or VHDL RTL design would be beneficial.
•Familiarity with financial pricing models and their implementation would be an advantage.
•Familiarity with big data, machine learning, genomics, PDE solving, matrix methods or other algorithmic implementation would be an advantage.
•Experience in the format and handling of market feed data in standard formats (e.g. FIX) would be an advantage.
•Familiarity with Xilinx tools (including Vivado, Vivado HLS, and SDx) would be an advantage.
•Good oral and written communication skills.
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