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Staff CAD Engineer (Static Timing Analysis)

157092
San Jose, CA, United States
Jul 9, 2019

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Job Description

Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology.  We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. 

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.  From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you!  At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work.  We are ONEXILINX.

Description

Xilinx is looking for a Staff CAD Engineer (Static Timing Analysis) in the IC CAD Team for the Central Engineering Group to support the design teams.


Responsibilities include:

  • Implement and support STA flows that design & integration teams use for timing verification.
  • Become a timing domain expert within the CAD team
  • Contribute to the execution and development of STA methodologies
  • Work directly with EDA vendors to address tool issues. 
  • Work closely with the design team to debug and resolve flow issues

  


 

Job Requirements

 

  • BS with 8+ yrs exp, MS with 6+ yrs exp or PhD with 3+ years of exp in Electrical Engineer, Computer Engineering or related equivalent
  • Proficiency in Perl and Tcl scripting is mandatory.  Prior background in developing EDA software is a plus
  • Expertise in Static Timing tools (for example: PrimeTime) is required
  • Experience in design methodologies with multi-voltage flows
  • Good understanding of STA concepts like crosstalk, noise, OCV
  • Experience in debugging STA issues related to parasitic extraction and back-annotation
  • Prefer prior experience in developing efficient PrimeTime tcl scripts  
  • Strong debugging skills. Ability to identify the root cause of issues and recommend fixes.
  • A good understanding of timing constraints, libraries is required
  • Good verbal and written communication skills with the ability to work with team members across multiple sites

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