Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
Xilinx is looking for a Staff CAD Engineer (STA) in the IC CAD Team for the Central Engineering Group to support the design teams.
- Implement and support STA flows that design & integration teams use for timing verification.
- Become a timing domain expert within the CAD team
- Contribute to the execution and development of STA methodologies
- Work directly with EDA vendors to address tool issues.
- Work closely with the design team to debug and resolve flow issues
- Proficiency in Perl and Tcl scripting is mandatory. Prior background in developing EDA software is a plus
- Expertise in Static Timing tools (for example: PrimeTime) is required
- Experience in design methodologies with multi-voltage flows
- Good understanding of STA concepts like crosstalk, noise, OCV
- Experience in debugging STA issues related to parasitic extraction and back-annotation
- Prefer prior experience in developing efficient PrimeTime tcl scripts
- Strong debugging skills. Ability to identify the root cause of issues and recommend fixes.
- A good understanding of timing constraints, libraries is required
- Good verbal and written communication skills with the ability to work with team members across multiple sites
Education Requirements, Experience
Masters in EE/CE with 6 years or PhD with 3 years of relevant experience.