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RTL SoC Integration Engineer - Staff

157086
San Jose, CA, United States
May 24, 2019

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Job Description

Description

Description
Xilinx has an opening for a Hardware Integration Engineer in the SOC Design team. This team is designing the silicon portion of Adaptable Compute Acceleration Platform.
 
In this highly visible role, you will:
  • Work in a cross-functional capacity with multiple teams across geographic locations
  • Construct and own sub-systems created from the full chip
  • Work with several verification and validation teams to develop test-benches around the sub-systems
  • Guide and review verification test plans/methodologies for the sub-systems
  • Collaborate with architecture to develop requirements for performance verification at sub-system level
  • Be responsible for the specification covering all integration and connectivity including both functional and test
  • Participate in silicon bring-up for sub-systems
  • Implement Automation to create sub-systems efficiently
 

 

 

#mh

Required Qualifications

  • BS with 8+ yrs or MS with 6+ yrs or PhD with 3+ yrs of experience in Electrical Engineering, Computer Science or related equivalent
  • Experience in integrating ASIC IP into SOC’s
  • Experience with chip-level integration of design blocks
  • Experience with “Physically Aware “ block integration
  • Understanding of AXI ARM protocol
  • Automation experience with scripting languages such as PERL, Python or TCL
  • Experience running standard quality checks such as Lint and CDC
  • Experience with multiple power domains including writing UPF
  • Simulation and associated debug experience
  • Experience with synthesis, static timing analysis & optimization
  • Experience writing timing constraints and exceptions in TCL or SDC syntax
  • Ability to develop clear and concise engineering documentation
  • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor
  • Excellent verbal and written communication skills
  • Excellent organizational skills and attention to detail
 
    • Desired Qualifications
      • Understanding of ARM architecture and APB, CHI protocols
      • Understanding of industry standard communication protocols such as PCIe
      • Experience in designing blocks for an SOC
      • Experience running automated quality checks on timing constraints
      • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
      • Experience working in design teams distributed over multiple sites
      • Post-silicon validation and debug experience
      • FPGA knowledge and emulation experience
      • Xilinx ISE or Vivado Design Suite and Xilinx Embedded Development Kit
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