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We have an opening for a Sr. Staff Design Engineer in the SoC Timing Team. This team is designing and analyzing the future generations high-performance FPGA that is combined with CPU and IO subsystems to give unparalleled flexibility to FPGA consumers
As a member of SoC Design and Integration team, you will:
- Own several full chip timing activities, including timing and noise closure for tapeout,
- Methodology development for Block level and Chip Level timing including, but not limited to constraints, budgeting, timing closure, data handoffs, margins, multi-scenario and timing-exceptions.
- Interface with various engineering groups, including design, CAD, software, and product engineering to guide design and analysis styles and review verification of blocks
- Develop/ enhance methodologies timing model generation and verification
- Debug design and flow issues related to Extraction, Noise, timing closure/ modeling/ constraint propagations, etc.
Common Essentials Duties and Responsibilities include, but not limited to:
- Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting)
- Creates and tracks schedules to ensure that component deliveries achieve technical and quality objectives per specifications in a timely manner
- Collaborates with design management and other engineering teams in identifying and addressing key areas where changes or the adaptation of methods is required to better align with Xilinx's needs
- Expert in technical innovation in the use of standard design implementation tools and methods (e.g. understands how to leverage the tool to have a positive impact on the design).
- Mentors junior design engineers on emerging methods and how best to integrate these into practice
Education and Experience Requirements:
- BS with 12+ years of relevant experience or MS with 8+ years of experience or PhD with 5+ years of experience in Electrical Engineering, Computer Engineering or Related Equivalent
- Basic knowledge of FPGA architecture
- Experience in RTL, synthesis, place and route, static timing analysis (STA) and electrical analysis.
- Fundamental static CMOS circuit design knowledge including simulation experience with Spice and Verilog
- Experience with Primetime, Goldtime, Tempus and/or other STA tools etc.
- Experience with high frequency, low power, multi-voltage design techniques
- Experience with automation using scripting techniques such as Perl, TCL, or Python
- Strong debugging skills
- Ability to develop clear and concise engineering documentation
- Excellent verbal and written communication and presentation skills
- Excellent organizational skills and attention to detail
- Leadership and mentorship skills
- Understanding of SOC Design and analysis techniques
- Experience with industry standard EDA tools for synthesis, place and route, electrical analysis, extraction.
- Experience with C/ C++
- Experience with Statistical Data analysis
- Experience managing projects and teams