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Design Engineer for Machine Learning Applications

156988
San Jose, CA, United States
Apr 15, 2019

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

Xilinx is seeking an FPGA design engineer to join our R&D team developing solutions for machine learning and Data Center acceleration. This is an opportunity to be on the ground-floor for the development of new hardware and software technology for accelerating data center workloads with a focus in particular on machine learning.
 
This role has an emphasis on the design and RTL coding of machine learning technology for the Xilinx next generation 7nm Versal platform.
 
Experience:
  • Experience with the design and RTL implementation of high-performance datapaths for FPGAs is core to the role.
  • FPGA design flows, timing closure, working with DDR memory, RTL coding, Vivado and in general design and verification methodologies for complex performance-optimized FPGA designs are central to this position. A strong knowledge of Python scripting and C coding is very beneficial.
  • Experience implementing digital signal processing algorithms, for example linear algebra functions, FFTs and other arithmetic functions in hardware is highly beneficial.

 

 
Skills – This candidate would have skills in several, but not necessarily all, of the following
  • Digital design
  • FPGA design flow
  • Verilog, System Verilog
  • Verification methodologies
  • Simulation using Questa, Vivado simulator and other simulators
  • Scripting languages such as python and tcl
  • Knowledge of machine learning datapath architecture would be beneficial
  • C/C++ programming skills would be beneficial

Education: 

  • MS in EE/CE + 6 years of experience;  PhD preferred
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