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Xilinx is seeking an FPGA design engineer to join our R&D team developing solutions for machine learning and Data Center acceleration. This is an opportunity to be on the ground-floor for the development of new hardware and software technology for accelerating data center workloads with a focus in particular on machine learning.
This role has an emphasis on the design and RTL coding of machine learning technology for the Xilinx next generation 7nm Versal platform.
- Experience with the design and RTL implementation of high-performance datapaths for FPGAs is core to the role.
FPGA design flows, timing closure, working with DDR memory, RTL coding, Vivado and in general design and verification methodologies for complex performance-optimized FPGA designs are central to this position. A strong knowledge of Python scripting and C coding is very beneficial.
Experience implementing digital signal processing algorithms, for example linear algebra functions, FFTs and other arithmetic functions in hardware is highly beneficial.
Skills – This candidate would have skills in several, but not necessarily all, of the following
FPGA design flow
Verilog, System Verilog
Simulation using Questa, Vivado simulator and other simulators
Scripting languages such as python and tcl
Knowledge of machine learning datapath architecture would be beneficial
C/C++ programming skills would be beneficial
- MS in EE/CE + 6 years of experience; PhD preferred