We are looking for a talented software engineer who can research and develop novel algorithms and techniques for Design Model (Netlist and Constraints) for our current Field Programmable Gate Array (FPGA) and Next-Generation Adaptable Computing Acceleration Platform (ACAP) architectures to significantly improve runtime performance and memory usage. The person will also be responsible with evaluating new architecture features and their impact on existing EDA tools and work with the field engineers on closing critical customer designs issues.
The person will design, develop, troubleshoot and debug software programs for enhancements and new products.
Job duties will include, but are not limited to:
- Develop core software infrastructure for Xilinx applications.
- Solve challenging technical problems with robust algorithms and features.
- Optimize code for high performance on large data sets and leverage leading edge industry standard technologies.
- Leverage EDA expertise to develop and maintain the core netlist and constraint infrastructure for Vivado Design Suite.
- Analyze the architecture and design of netlist/constraint infrastructure to support new FPGA and ACAP devices.
- Apply software architecture skills to improve the runtime and memory footprint of the netlist/constraint infrastructure.
- Utilize EDA knowledge to ensure that the infrastructure supports Xilinx EDA tools like synthesis, placer and router.
- Enable runtime efficient import and export operations on the netlist/constraint database.
- Utilize strong analytical and troubleshooting skills along with the EDA flow knowledge to maintain and help re-architect the netlist/constraint infrastructure to the next level.
Knowledge of Data structures, Graph Theory and Algorithms.
VHDL, Verilog, or EDIF
Experience with FPGA or ASIC design flows is a plus
Experience with scripting languages (TCL, Perl, or Python) is a plus
BS in EE/CE/CS with +9 years, OR
MS in EE/CE/CS with +7 years, OR
PhD in EE/CE/CS +4 years of relevant industry experience