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Staff Design Engineer

Hyderabad, India, India
Sep 6, 2019


Job Description


Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

This opening is an exciting opportunity to work for a new Xilinx DFT team in Hyderabad. As Staff DFT Engineer, candidate will lead a team of DFT engineers to work on Scan, MBIST, iJTAG verification and Silicon bring up on the state of the art IPs in 7nm process and beyond. The IPs range from ARM based Processor to critical IPs which provide automotive, data centre, machine learning and high speed communication solutions. Candidate will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects.:

Key responsibilities include but are not limited to:

 . Work closely with design team and make sure DFT structures are correctly inserted.

.  Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.

.  Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models

.  Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, 1149.1 JTAG and IJTAG

.  Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE

.  Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem

.  Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

· BS/MS EE with relevant logic design/test background. 8-10 years’ work experience as a DFT Engineer

.  Experience in DFT implementation including Scan and Scan Compression at IP and SoC level

.  Proficient in logic design using Verilog and experience in synthesis and STA

.  Experience in developing test benches and simulation in RTL/GATE/SDF environments

.  Good communication skill and has to be able to works well in a group environment that spans across continents

.  Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay), scan compression. Knowledge of MBIST is a plus.

.  Knowledge of FPGA synthesis and design flow is a plus

.  Perl, shell scripting skills as well as Linux OS environment are assumed

Refer to the Talent Network

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